The present invention relates to a byte-wide building block which may be connected to three bidirectional buses and serve as a memory interface device or a processor.
Improved fabrication techniques have led to the development of very large scale integrated circuits suitable for use in data processors. Because of the relatively low cost and small size, it has been customary to build modular integrated circuits capable of performing a plurality of functions and being programmable for specific applications. The modules are frequently built as byte wide blocks capable of handling operands of 8-bits plus a parity bit. The modules are usually provided with pin connections for connection to two or more buses which may or may not be bidirectional buses. One module of the prior art is capable of receiving operands on two input buses, performing an arithmetic or logical operation on the operands, and presenting the result to an output bus within one microcycle or one clock pulse interval. However, insofar as is known to applicants, no module of the prior art is capable of receiving an operand from a given bus, performing an arithmetic or logical operation on that operand, and returning the result of the operation to the same bus as well as other buses during the same microcycle.
Error checking and correcting codes are known in the prior art. In a typical code, particular bits of a multi-byte word are exclusively ORed to produce a multibit check byte. The check byte may be stored in the memory along with the word with which it is associated. On read out from the memory a new check byte is generated from the data and compared with the check byte retrieved from the memory. If only a single error has occurred it can be detected and corrected or, if multiple errors have occurred they may be detected.
Because the error correcting code check bits for each byte result from an exclusive OR of different sets of data bits in each of the bytes of a multi-byte word, it has been customary in the past to provide a specialized module for handling the error checking and correction operations. The use of a specialized module detracts from the overall modularity of a system and it is desirable that the error checking and correcting capabilities be provided by modular circuits which may be identical for each byte of a multi-byte word.